德国TU Darmstadt人工智能硬件中心(Hardware for AI)博士招生信息
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德国TU Darmstadt 人工智能硬件中心(etit.tu-darmstadt.de招收4名硕士毕业生（已经毕业或者2025年底毕业）攻读博士。研究方向为 (1)基于数字电路的低功耗神经网络加速器设计 (2) 基于RRAM/memristor和数字电路的混合神经网络加速器 (3) 神经网络在CPU上的高速执行 (4)神经网络的逻辑可解释。招生要求为具有神经网络和硬件电路设计方法基础。具体信息请参考文件底部的英文介绍。此职位净收入约为每月2800欧元 (TV-L E13 100%)。博士研究开始时间为2026年一月。
TU Darmstadt位于黑森州达姆施塔特,是德国历史悠久的理工大学。它是德国九所卓越理工大学联盟TU9成员之一，两次入选德国大学卓越计划。1882年，世界第一个电气工程系在TU Darmstadt成立。TU Darmstadt在德国电子与电气工程、人工智能、机器学习、深度学习、机器人技术、计算机视觉和自然语言处理领域名列前茅。
TU Darmstadt人工智能硬件中心主任Prof.Dr.-Ing.Li Zhang (hwai.tu-darmstadt.de 于2022年10月入职 TU Darmstadt电子工程和信息技术系。她是德国在集成电路和人工智能领域的首位华人教授。她曾获得德国工程师协会Dr. Wilhelmy Preis，为2019年度德国所有工程领域三位得主之一，并且是该奖首位中国学者得主。她还获得了慕尼黑工业大学电子与计算机工程系Walter Gademann Preis，以奖励她在电路设计方法学上的突出贡献。
在TU Darmstadt人工智能硬件中心攻读博士为英文交流，无需德语。对此职位感兴趣者请联系Prof. Dr.-Ing. Li Zhang ([email protected])。请将本人CV, 1point3acres.com.
PhD1: Energy-efficient digital AI accelerators
The existing research on digital neural network accelerators primarily focuses on hardware architectures and complexity reduction of MAC operations. However, further specifications of hardware, e.g., power, timing, and area constraint, have not yet been considered systematically in existing solutions. Consequently, the resulting designs may still be suboptimal in practice, e.g., violating power and area specifications. In this project, we will explore the codesign of hardware and neural networks from the perspective of circuit design methodologies to consider power, performance and area simultaneously. These hardware properties will be incorporated into the design process of neural networks to avoid potential compromise when neural networks are mapped onto hardware. The resulting hardware will also have the flexibility to deal with irregular matrix sizes and skip unnecessary operations in neural networks, so that a high overall computational efficiency can be achieved.
PhD2: hybrid analog and digital AI accelerators
In this project, pwe will address the challenges in integrating RRAM-based designs into modern systems to fully unleash the potential of emerging devices in enhancing the computational and energy efficiency for AI applications. These challenges include RRAM device and array issues, e.g., variations, programming and IR drop, synergistic cooperation with digital designs, e.g., systolic arrays, digital interface to RRAM-designs as well as task distribution into analog and digital domains at system level, which prevent their large-scale integration into computing systems. To address these challenges, at hardware level, the measurement of RRAM arrays will be used to establish RRAM device models under variations, drifting, faults and aging and to analyze IR-drop, with which methodologies to counter such effects will be developed to enhance their robustness and reliability. Reprogramming-free algorithms will also be created to avoid time-consuming reprogramming process in RRAM-based designs. To further compensate computational accuracy degradation of RRAM-based designs, analog-aware digital designs will be used to work with RRAM-based designs in a hybrid way. At the system level, computational tasks will be automatically partitioned and allocated into digital designs and RRAM-based designs to balance computational accuracy and energy efficiency. The developed methodologies, which will be released as open-source tools, will be verified using the example of neural networks including large language models on a demonstrator consisting of manufactured RRAM arrays and digital designs with FPGA emulations to demonstrate the application of this project result in AI-driven healthcare products and sensor as well as IoT products. The tools developed in this project bridge the development of emerging devices, which are not limited to RRAM devices, and their practical integration into computing systems. As a result, the tools eliminate the requirement of understanding low-level analog details by system engineers to make RRAM-based designs more accessible to various applications and thus reduce design developments costs and time to market for SMEs.
PhD3 Efficient execution of neural networks on CPUs for edge devices
PhD4: Uncovering logic reasoning of deep neural networks
Deep neural networks (DNNs) have achieved great breakthroughs in many fields. However, DNNs require massive multiply-accumulate (MAC) operations and their execution on digital hardware causes formidable energy consumption. State-of-the-art solutions are still focusing on simply accelerating MAC operations in DNNs instead of examining their actual logic functions after training. The blind execution of massive MAC operations in inference, however, poses critical risks to performance and energy sustainability of AI systems. It also misses the opportunity of examining internal decision-making processes of DNNs for their verification
in reliability-critical systems. To address these challenges, LogiNet explores a new perspective to study the execution of DNNs on hardware with their logic representations and high-level expressions, thus opening a new door for design methodologies to realize high-performance and low-energy DNN computing for a wide range of scenarios from edge devices to data centers. The high-level expressions of DNNs can also be used to analyze the properties of DNNs and thus contribute to the understanding of their actual functions. Specifically, LogiNet extracts logic representations of DNNs by embedding pretrained weights into the circuits of MAC operations to reduce data movement and computational complexity. This also constructs a bridge between MAC operations and their high-level expressions, which can be compiled and executed by CPUs and thus enable a flexible scheduling of DNN operations in modern heterogeneous computing systems. Furthermore, LogiNet explores the analysis of DNN properties such as hardware reliability and fairness in decision-making using high-level expressions. In short, LogiNet not only develops new solutions for green AI to benefit economy and environment but also lays the foundation for new directions such as logic-based DNN validation in the era of large-scale models that have started to influence our society fundamentally.
TU Darmstadt位于黑森州达姆施塔特,是德国历史悠久的理工大学。它是德国九所卓越理工大学联盟TU9成员之一，两次入选德国大学卓越计划。1882年，世界第一个电气工程系在TU Darmstadt成立。TU Darmstadt在德国电子与电气工程、人工智能、机器学习、深度学习、机器人技术、计算机视觉和自然语言处理领域名列前茅。
TU Darmstadt人工智能硬件中心主任Prof.Dr.-Ing.Li Zhang (hwai.tu-darmstadt.de 于2022年10月入职 TU Darmstadt电子工程和信息技术系。她是德国在集成电路和人工智能领域的首位华人教授。她曾获得德国工程师协会Dr. Wilhelmy Preis，为2019年度德国所有工程领域三位得主之一，并且是该奖首位中国学者得主。她还获得了慕尼黑工业大学电子与计算机工程系Walter Gademann Preis，以奖励她在电路设计方法学上的突出贡献。
在TU Darmstadt人工智能硬件中心攻读博士为英文交流，无需德语。对此职位感兴趣者请联系Prof. Dr.-Ing. Li Zhang ([email protected])。请将本人CV, 1point3acres.com.
PhD1: Energy-efficient digital AI accelerators
The existing research on digital neural network accelerators primarily focuses on hardware architectures and complexity reduction of MAC operations. However, further specifications of hardware, e.g., power, timing, and area constraint, have not yet been considered systematically in existing solutions. Consequently, the resulting designs may still be suboptimal in practice, e.g., violating power and area specifications. In this project, we will explore the codesign of hardware and neural networks from the perspective of circuit design methodologies to consider power, performance and area simultaneously. These hardware properties will be incorporated into the design process of neural networks to avoid potential compromise when neural networks are mapped onto hardware. The resulting hardware will also have the flexibility to deal with irregular matrix sizes and skip unnecessary operations in neural networks, so that a high overall computational efficiency can be achieved.
PhD2: hybrid analog and digital AI accelerators
In this project, pwe will address the challenges in integrating RRAM-based designs into modern systems to fully unleash the potential of emerging devices in enhancing the computational and energy efficiency for AI applications. These challenges include RRAM device and array issues, e.g., variations, programming and IR drop, synergistic cooperation with digital designs, e.g., systolic arrays, digital interface to RRAM-designs as well as task distribution into analog and digital domains at system level, which prevent their large-scale integration into computing systems. To address these challenges, at hardware level, the measurement of RRAM arrays will be used to establish RRAM device models under variations, drifting, faults and aging and to analyze IR-drop, with which methodologies to counter such effects will be developed to enhance their robustness and reliability. Reprogramming-free algorithms will also be created to avoid time-consuming reprogramming process in RRAM-based designs. To further compensate computational accuracy degradation of RRAM-based designs, analog-aware digital designs will be used to work with RRAM-based designs in a hybrid way. At the system level, computational tasks will be automatically partitioned and allocated into digital designs and RRAM-based designs to balance computational accuracy and energy efficiency. The developed methodologies, which will be released as open-source tools, will be verified using the example of neural networks including large language models on a demonstrator consisting of manufactured RRAM arrays and digital designs with FPGA emulations to demonstrate the application of this project result in AI-driven healthcare products and sensor as well as IoT products. The tools developed in this project bridge the development of emerging devices, which are not limited to RRAM devices, and their practical integration into computing systems. As a result, the tools eliminate the requirement of understanding low-level analog details by system engineers to make RRAM-based designs more accessible to various applications and thus reduce design developments costs and time to market for SMEs.
PhD3 Efficient execution of neural networks on CPUs for edge devices
PhD4: Uncovering logic reasoning of deep neural networks
Deep neural networks (DNNs) have achieved great breakthroughs in many fields. However, DNNs require massive multiply-accumulate (MAC) operations and their execution on digital hardware causes formidable energy consumption. State-of-the-art solutions are still focusing on simply accelerating MAC operations in DNNs instead of examining their actual logic functions after training. The blind execution of massive MAC operations in inference, however, poses critical risks to performance and energy sustainability of AI systems. It also misses the opportunity of examining internal decision-making processes of DNNs for their verification
in reliability-critical systems. To address these challenges, LogiNet explores a new perspective to study the execution of DNNs on hardware with their logic representations and high-level expressions, thus opening a new door for design methodologies to realize high-performance and low-energy DNN computing for a wide range of scenarios from edge devices to data centers. The high-level expressions of DNNs can also be used to analyze the properties of DNNs and thus contribute to the understanding of their actual functions. Specifically, LogiNet extracts logic representations of DNNs by embedding pretrained weights into the circuits of MAC operations to reduce data movement and computational complexity. This also constructs a bridge between MAC operations and their high-level expressions, which can be compiled and executed by CPUs and thus enable a flexible scheduling of DNN operations in modern heterogeneous computing systems. Furthermore, LogiNet explores the analysis of DNN properties such as hardware reliability and fairness in decision-making using high-level expressions. In short, LogiNet not only develops new solutions for green AI to benefit economy and environment but also lays the foundation for new directions such as logic-based DNN validation in the era of large-scale models that have started to influence our society fundamentally.
